器件名称:
M74HC109
功能描述:
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
文件大小:
187.76KB 共12页
简 介:
M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR s s s s s s s HIGH SPEED : fMAX = 67MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 109 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC109B1R M74HC109M1R T&R M74HC109RM13TR M74HC109TTR DESCRIPTION The M74HC109 is an high speed CMOS DUAL J-K FLIP FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. In accordance with the logic level on the J and K input this device changes state on positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC109 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1,15 2, 14, 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 SYMBOL 1CLR, 2CLR 1J, 2J, 1K, 2K 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND Vcc NAME AND FUNCTION Asynchronous Reset Direct Input Synchronous Inputs; Flip-Flops 1 and 2 Clock Input Asynchronous Set Direct Input (Active Low) True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS CL……
