器件名称:
M74HC73
功能描述:
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
文件大小:
247.47KB 共11页
简 介:
M54HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS73 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC73F1R M74HC73M1R M74HC73B1R M74HC73C1R DESCRIPTION The M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Depending on the logic level applied to J and K inputs, this device changes state on the negative going transition of clock input pulse (CK). The clear function is accomplished independently of the clock condition when the clear input (CLR) is taken low. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74HC73 TRUTH TABLE INPUTS CLR L H H H H H X: Don’t Care OUTPUTS K X L H L H X CK X Q L Qn L H Qn Qn Q H Qn H L Qn Qn J X L L H H X FUNCTION CLEAR NO CHANGE --TOGGLE NO CHANGE PIN DESCRIPTION PIN No 1, 5……
