器件名称:
M12S16161A
功能描述:
512K x 16Bit x 2Banks Synchronous DRAM
文件大小:
613.51KB 共29页
简 介:
ESMT SDRAM M12S16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 32ms refresh period (2K cycle) GENERAL DESCRIPTION The M12S16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. z z z z z ORDERING INFORMATION Part NO. M12S16161A-7TG M12S16161A-7BG MAX Freq. 143MHz 143MHz PACKAGE COMMENTS 50 TSOP(II) VFBGA Pb-free Pb-free PIN CONFIGURATION (TOP VIEW) 1 A VSS 2 DQ15 3 4 5 6 DQ0 7 VDD VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSS……
