器件名称:
MC100E155FN
功能描述:
6-BIT 2:1 MUX-LATCH
文件大小:
105.49KB 共4页
简 介:
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6Bit 2:1 MuxLatch The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. MC10E155 MC100E155 6-BIT 2:1 MUX-LATCH 850ps Max. LEN to Output 825ps Max. D to Output Single-Ended Outputs Asynchronous Master Reset Dual Latch-Enables Extended 100E VEE Range of – 4.2V to – 5.46V 75k Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) D5a 25 D5b LEN1 LEN2 VEE MR SEL D0a 26 27 28 1 2 3 4 5 D0b 6 D1a 7 D1b 8 D2a 9 10 11 Q0 D3a D3b D4b 24 D4a 23 D3b 22 D3a 21 NC 20 VCCO 19 18 17 16 15 14 13 12 Q5 Q4 VCC Q3 Q2 VCCO Q1 D0a D0b D1a D1b D2a D2b FN SUFFIX PLASTIC PACKAGE CASE 776-02 LOGIC DIAGRAM Q MUX SEL MUX SEL D EN R Q0 Q D EN R Q1 MUX SEL MUX SEL MUX SEL MUX SEL Q D EN R Q2 D2b VCCO Q D EN R * All VCC and VCCO pins are tied together on the die. Q3 PIN NAMES Pin D0a – D04 D0b – D4b SEL LEN1, LEN2 MR Q0 – Q4 Function Input Data a Input Data b Data Select Input Latch Enables Master Reset Outputs D4a D4b D5a D5b SEL LEN1 LEN2 MR D EN R Q Q4 D EN R Q Q5 TRUTH TABLE SEL H L 5/95 Data a b Motorola, Inc. 1996 2–1 REV 3 MC10E155 MC100E155 DC CHARACTERISTICS (VEE = VEE(min) to VEE(ma……
