器件名称:
MC100E155FN
功能描述:
5V ECL 6Bit 2:1 MuxLatch
文件大小:
126.97KB 共8页
简 介:
MC10E155, MC100E155 5V ECL 6Bit 2:1 MuxLatch Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with singleended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. The 100 Series contains temperature compensation. Features http://onsemi.com 850 ps Max. LEN to Output 825 ps Max. D to Output SingleEnded Outputs Asynchronous Master Reset Dual LatchEnables PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = 4.2 V to 5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 PbFree = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 239 Devices PbFree Packages are Available* PLCC28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MCxxxE155FNG AWLYYWW xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the ……
