器件名称:
MC74HCT373
功能描述:
Octal 3-State Noninverting Transceiver Latch with LSTTL-Compatible Inputs
文件大小:
185.14KB 共8页
简 介:
MC74HCT373A Octal 3-State Noninverting Transparent Latch with LSTTL-Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT373A may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs. The HCT373A is identical in pinout to the LS373. The eight latches of the HCT373A are transparent D–type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched. The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high–impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT373A is identical in function to the HCT573A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT533A, which has inverting outputs. http://onsemi.com MARKING DIAGRAMS 20 PDIP–20 N SUFFIX CASE 738 1 MC74HCT373AN AWLYYWW 1 20 20 20 1 SOIC WIDE–20 DW SUFFIX CASE 751D 1 TSSOP–20 DT SUFFIX CASE 948G HCT373A AWLYYWW 20 HCT 373A ALYW 1 20 1 Output Drive Capability: 15 LSTTL Loads TTL/NMOS–Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 196 FETs or 49 Equivalent Gates A WL YY WW = Assembly Location = Wafer Lot = Year……
