器件名称:
CD54HC280F3A
功能描述:
High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker
文件大小:
261.91KB 共9页
简 介:
CD54HC280, CD74HC280, CD54HCT280, CD74HCT280 Data sheet acquired from Harris Semiconductor SCHS175D November 1997 - Revised October 2003 High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker Description The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator checker devices. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (ΣE output is high) when an even number of data inputs is high. Odd parity is indicated (ΣO output is high) when an odd number of data inputs is high. Parity checking for words larger than 9 bits can be accomplished by tying the ΣE output to any input of an additional HC/HCT280 parity checker. Features [ /Title (CD74 HC280 , CD74 HCT28 0) /Subject (High Speed CMOS Logic 9-Bit Odd/E ven Parity Typical Propagation Delay = 17ns at VCC = 5V, CL = 15pF, TA = 25oC Replaces LS180 Types Easily Cascadable Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1A at VOL, ……
